The present disclosure relates to overlay metrology.
As technology advances, the integrated circuit (IC) industry has experienced exponential growth. Technological advances in layering, patterning and doping operations have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density, such as the number of interconnected devices, has generally increased while geometry size has decreased. Meanwhile, a wafer size has increased for manufacturing more ICs on one single wafer. Thus during fabrication of semiconductor devices, each patterned layer has to be aligned with a previous patterned layer.
Currently, the alignment precision is measured as overlay offset or overlay error. The overlay is the relative position between two or more layers of a wafer. As semiconductor processes evolve to provide for smaller critical dimensions, and devices reduce in size and increase in complexity including number of layers, the alignment precision between layers becomes increasingly more important to the quality, reliability, and yield of the devices. Misalignment of layers can cause performance issues and even potentially causing a device to fail due to, for example, a short caused by a misaligned interconnect layer.